Pedestrian Detection Image Processing with FPGA

This paper focuses on real-time pedestrian detection using the Histograms of Oriented Gradients (HOG) feature descriptor algorithm in combination with a Linear Support Vector Machine (LSVM) on a Field Programmable Gate Array (FPGA). Pedestrian detection on embedded systems is a challenging problem since accurate recognition requires extensive computation. To achieve real-time pedestrian recognition on embedded systems, hardware architecture suitable for HOG feature extraction is proposed. HOG is considered the most accurate pedestrian detection algorithm in modern computer vision. In order to reduce computational complexity toward efficient hardware architecture, this paper proposes several methods to simplify the computation of the HOG feature descriptor such as conversion of the division, square root, and arctangent to more simple operations. The architecture is proposed on a Xilinx Zynq-7000 All Programmable SoC ZC702 using Verilog HDL to evaluate the real-time performance. This implementation processes image data at twice the pixel rate of similar software simulations and significantly reduces resource utilization while maintaining high detection accuracy. iii Acknowledgements